What is MMIO address space?
MMIO address space of an IO device is the range of the address space which falls under the same range where computer's main memory is mapped. Operating system or BIOS maps device MMIO memory in the region where system main memory or RAM is located. This region is either below of above the region of RAM and never overlaps. Main CPU access these device mapped regions in the same way as it access the main memory. MEMRD and MEMWR pins are used to read and write MMIO address space.
What is IO address?
x86, Atmel and some other architecture have a special address space region for IO devices. This region is similar to memory mapped region but falls under in a different address space. This is accessed via a special instructions called IN and OUT and this is limited to max 16bit address. Thus only 64Kb of memory is available and it is not overlapped with main memory area. A pair of pins IOR and IOW are activated during the access of this IO address space. MEMRD/MEMWR are not activated during IO memory access.
What is Interrupt and IRQ line ?
Interrupt is a mechanism from the I/O device to notify the CPU that it has performed some task. A pair of pins INTR and INTA are used for this mechanism. INTR is the interrupt request line. This is asserted by IO device and CPU takes action. CPU then jumps to special routine known as interrupt service routine. Once routine is finished its job is to assert the INTA line. INTA is the interrupt acknowledgment line. It is to tell the interrupt controller chip that CPU has performed the task for the particular interrupt.
What is Interrupt request line or IRQ line?
There could be several INTR lines from IO devices and they can perform an interrupt at the same time. So the pair of INTR and INTA pins in CPU cannot differentiate the IO devices which has performed the interrupt. Programmable Interrupt controller chip or PIC chip is used in between CPU and IO devices. x86 architecture uses 8259A IC which known as programmable interrupt controller PIC. APIC or advanced It has 8-16 or 24 lines to take the individual interrupts from the IO devices. These lines are called interrupt request lines or IRQ lines.
How IRQ Chip delivers the interrupts from different devices?Device asserts individual IRQ lines. IRQ chip asserts the INTR line along with the IRQ line details to the CPU. CPU uses this IRQ line parameter to decide which interrupt to serve. Once the service is done CPU asserts INTA/acknowledgment. Then IRQ Chip can further assert the INTR for the next pending IRQs.
Now there can be interrupt requests from two or more devices in parallel. In that case IRQ chip maintains a list called interrupt priority list. IRQ chip decides which interrupt should be served first. Depending on the priorities IRQ chip decides which interrupt to serve first.
What is PCI Interrupt pin?
PCI uses 4 IRQ lines for selecting the IRQs for the PCI slot. These are named as INTA, INTB, INTC, INTD. Interrupt pin field in PCI config address space determines this value. There could be more than four PCI slots in a motherboard. So IRQ PINS and irq lines are shared between two or more devices. This is called shared interrupt. This field is 8 bit so extended PCI decides to put four more IRQ lines named as INTE, INTF, INTG, INTH. So total 8 pins are possible and PCI device should use at least one.
What are base address registers or BAR in PCI?
Base address registers or BARs are six 32bit fields in PCI configuration address space which is used to map MMIO and IO addresses of the device. These MMIO and IO addresses are the data communication window between host CPU and PCI device. Initially it was designed to map only 32bit MMIO addresses later two BARs where clubbed together to define a 64bit BAR. BIOS or OS writes the memory address to the BARs and activates using command register. Device has to respond to host CPU's read and write cycles when it falls under the BAR address range.
How Plug and Play mechanism works in PCI?
Plug and Play mechanism describes how host softwares like BIOS or Operating system should fetch the attributes from the device and then programs the IO parameters to the device. Plug and Play mechanism reduces manual effort of manipulating jumpers on the motherboard when a new PCI card is added. It detects the card presence and reads attributes of the device and then programs the IO parameters. This phase is known as PCI enumeration and configuration phase.
PCI design treats all the IO device should have a configuration space. Host CPU has root complex which seats in the top of the hierarchy. Now root has several ports or slots or bridges for IO devices.
We are taking one example of a device which is connected directly to root bridge. Configuration software (BIOS/OS) first programs a secondary bus and a subordinate bus. secondary bus is often taken as primary bus +1 . It checks the Vendor ID and device ID of the child card on secondary bus/Device 0/Function 0. Once these are valid values then other fields like class, Sub-vendor, Sub-Device IDs etc are fetched. Now Configuration software checks BAR registers. All 1s or 0xFFFFFFFF is written to each BARs and value is read back. This gives the size of the BAR address. Now MMIO or IO address is programmed back to the BAR register. Addresses are sequential allocated and they are unique for each device and even different BARs in the same card. MMIO address has two ranges one is below 4GB for 32 bit BARs and another above 4GB which is for 64bit BARs. This 64bit BARs are allocated above maximum RAM supported by the CPu memory controller.
Now for example IO base is 2Kb, MMIO 32 base start is 2GB and MMIO 64 base is 4TB. Now we have a card which has two functions,
Card#1 (secondary bus/Device 0/Function 0) BAR#1 size = 1K, type IO BAR#2 size = 1MB, type MMIO 32 BAR#3 size 64MB, type MMIO 64 BAR#1 = 2Kb BAR#2 = 2GB BAR#3 = 4TB Card#2(secondary bus/Device 0/Function 1) BAR#1 size = 4K, type IO BAR#2 size = 1MB, type MMIO 32 BAR#3 size 1MB, type MMIO 64 BAR#1 = 2Kb+1KB BAR#2 = 2GB+1MB BAR#3 = 4TB+64Mb
IRQ lines and PINs are maintained from the Slot or bridge config space. Once operating system loads the device drivers it installs interrupt handlers for these IRQ lines.
The enumeration repeats for the max functions (0-15) and device ranges (0-31).
Similar topics related to this section
BIOS, Booting, PC Firmare, Topics Index, Primary Base Memory, High, Extended Memory and IO Ports, Memory Mapped IO Layout, IO Port Ranges, Interrupt Lines, x86 Registers, Real Mode Memory Segmentation, Power On Self Test, H/W Inits, Software Interrupts, Keyboard Module and int16, VGA Display int10, Disk Subsystem int13, BIOS Config Screen, BIOS Development Code Flashing Debugging, Plug-n-Play, PCI card PnP Mechanism, PCI Config Address Space, PCI MMIO IO IRQ perations, BIOS Boot OPROMs Drivers, Disk Cylinder Head Sectors, MBR Disk Partitions, MBR and File Allocation Table Partitions, Boot Loader, Grand Universal Bootloader Linux Booting, NT Loader Windows Booting, Embedded System Booting, Unified Extensible Firmware Interface Stack, UEFI Development And Advantages, References and Links,