IO Port Ranges

What is IO memory (IO ports) address in x86? 

IO memory is a special address space used for the mutual interaction with IO devices. In early stages of ISA bus design, MMIO range was limited to 20 bits and thus limited to an upper limit of 1MB. This range has to accommodate main memory of RAM and ROM.

RAM used to take a range of 0-9FFFF. BIOS and plug-in ROMs used to take the range of C0000-FFFFF. VGA frame buffer MMIO range used to take 128kb in the range of A0000-BFFFF.   Therefore there was not much range to map device IO areas. Device IO used to mapped to a separate address space. This address space is known as IO memory range.

This has a width of 16bit in address thus can be in the ranged from 0 to FFFF or upto 64Kb. CPU does not directly access this using pointer or MOV instruction. There is a special instruction pair known as IN and OUT to access this memory range. 

What are the assembly instructions for accessing IO ports?

IN and OUT instructions are the base instructions for reading or writing IO address space. Data width can be in the range of byte, word, long etc. GCC assembly used to take a suffix of b/w/l for these accordingly.

  • inb/inw/inl - Instructions to read byte/word/long from IO ports
  • outb/outw/outl - Instructions to write byte/word/long to IO ports

A block of bytes can be read or write from or to IO memory using repetitive string instructions. These are often used in older type of block devices or multimedia devices.

  • insb/insw/insl - Instructions to read a block of bytes/words/longs from IO ports and the number of counts should be in CX register.
  • outsb/outsw/outsl  - Instructions to write a block of bytes/words/longs to IO ports and the number of counts should be in CX register.

What are the C functions for accessing IO ports?

C IO library function wraps these above inline assembly to C inline functions. DOS Turbo C and Windows/Linux have C corresponding heads and libraries.

#include <sys/io.h>

unsigned char inb(unsigned short int port);
unsigned char inb_p(unsigned short int port);
unsigned short int inw(unsigned short int port);
unsigned short int inw_p(unsigned short int port);
unsigned int inl(unsigned short int port);
unsigned int inl_p(unsigned short int port);

void outb(unsigned char value, unsigned short int port);
void outb_p(unsigned char value, unsigned short int port);
void outw(unsigned short int value, unsigned short int port);
void outw_p(unsigned short int value, unsigned short int port);
void outl(unsigned int value, unsigned short int port);
void outl_p(unsigned int value, unsigned short int port);

void insb(unsigned short int port, void *addr,
		  unsigned long int count);
void insw(unsigned short int port, void *addr,
		  unsigned long int count);
void insl(unsigned short int port, void *addr,
		  unsigned long int count);
void outsb(unsigned short int port, const void *addr,
		  unsigned long int count);
void outsw(unsigned short int port, const void *addr,
		  unsigned long int count);
void outsl(unsigned short int port, const void *addr,
		  unsigned long int count);

Is there any overlap of address space between IO memory and MMIO?

Both IO memory and MMIO can range from 0 - 64kb and 0-1MB but they are not overlapped.

How CPU tells the memory and peripheral devices that operation is for I/O port or Memory ?

There is a pin used to indicate if the address bus is holding the address of memory mapped region or I/O port regions. This pin named as Mem/IO, when it is 1, this tells CPU is using memory region. When this is zero it is for the IO port operation. There is another pin named as W/R (Write/read). When W/R is 1, it is a write operation, when W/R is zero it is read operation. There are 4 combinations possible-

  1. Memory Write (Mem/IO = 1, W/R = 1)
  2. Memory Read (Mem/IO = 1, W/R = 0)
  3. I/O Write (Mem/IO = 0, W/R = 1)
  4. I/O Read (Mem/IO = 1, W/R = 0)
Some PCI devices use both MMIO and IO mem for the device operations. So these devices use both Mem/IO = 1 and Mem/IO = 0. This type of PCI devices implement both MMIO and IO mem type BAR registers. Device driver use PCI command bits to activate either MMIO or IO MEM mode. Then corresponding BAR registers are used for IO operations.

What is super IO chip on motherboard?

Super IO chip is an integrated circuit on the motherboard which houses all the legacy IO devices like serial port, parallel port, PS/2 keyboard and mouse controller etc. Earlier days when ISA bus was a standard, each IO device has to be plugged-in in the board. Later it become essential to have all the devices on the mother board.

What are the very commonly mapped IO devices and their IO ranges?

====Port range==== ===Summary====
0x0000-0x001F The first legacy DMA controller, often used for transfers to floppies.
0x0020-0x0021 The first Programmable Interrupt Controller
0x0022-0x0023 Access to the Model-Specific Registers of Cyrix processors.
0x0040-0x0047 The PIT (Programmable Interval Timer)
0x0060-0x0064 The "8042" PS/2 Controller or its predecessors, dealing with keyboards and mice.
0x0070-0x0071 The CMOS and RTC registers
0x0080-0x008F The DMA (Page registers)
0x0092 The location of the fast A20 gate register
0x00A0-0x00A1 The second PIC
0x00C0-0x00DF The second DMA controller, often used for soundblasters
0x00E9 Home of the Port E9 Hack. Used on some emulators to directly send text to the hosts' console.
0x0170-0x0177 The secondary ATA harddisk controller.
0x01F0-0x01F7 The primary ATA harddisk controller.
0x0278-0x027A Parallel port
0x02F8-0x02FF Second serial port
0x03B0-0x03DF The range used for the IBM VGA, its direct predecessors, as well as any modern video card in legacy mode.
0x03F0-0x03F7 Floppy disk controller
0x03F8-0x03FF First serial port

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BIOS, Booting, PC Firmare, Topics Index, Primary Base Memory, High, Extended Memory and IO Ports, Memory Mapped IO Layout, IO Port Ranges, Interrupt Lines, x86 Registers, Real Mode Memory Segmentation, Power On Self Test, H/W Inits, Software Interrupts, Keyboard Module and int16, VGA Display int10, Disk Subsystem int13, BIOS Config Screen, BIOS Development Code Flashing Debugging, Plug-n-Play, PCI card PnP Mechanism, PCI Config Address Space, PCI MMIO IO IRQ perations, BIOS Boot OPROMs Drivers, Disk Cylinder Head Sectors, MBR Disk Partitions, MBR and File Allocation Table Partitions, Boot Loader, Grand Universal Bootloader Linux Booting, NT Loader Windows Booting, Embedded System Booting, Unified Extensible Firmware Interface Stack, UEFI Development And Advantages, References and Links,