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ARM has 32bit address bus(LADDR0-31) and 32 bit data bus [LDATA0-31]. Along with this ARM has control bus lines.

  • 11 LnOE - read enable
  • 12 LnWE - write enable
  • 13 nWAIT - wait from device
  • 14 nRESET - reset
  • 16 nXDREQ0 DMA request
  • 15 nXDACK0 - DMA Acknowledge
  • Interrupt Interrupt pins
Interaction between CPU and peripheral happens between address and data lines. There are normal read/write or DMA oriented transfer. We will discuss only normal register read/write transfers.

Address Data and Control lines

Data bus is 32bit thus register transfer can be at a maximum of 32bits in one transaction. Read enable, Write enable and wait are major control lines used in these operations. CPU initiates read or write by pulling down either of the line voltage. Note here read or write is inverted signal/negative logic lines. CPU will set these to zero to indicate these as either read or write. Now peripherals are generally slow devices. It cannot serve data thus wait line is used to do a flow control. Wait signal is also inverted signal/negative logic. Device sets this to zero when ready to provide data or ready to collect date. In our next section we will describe these by means of timing diagrams.

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Altera FPGA interfacing ARM, ARM CPU internals, ARM CPU, Cache Memory and MMU, ARM bus hierarchy, ARM data, address and control lines, ARM MMIO read, ARM MMIO write, FPGA interfacing with system bus, VHDL/Verilog program, ADS C Code, Linux Direct MMIO App, Linux Device Driver, Linux Application code, Final Demo,

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