Read operations starts from CPU with instruction like load (ldrb). With a rising edge of hclk/pclk CPU places address to address bus and pulls down read enable line nOE. This way CPU tells it wants to read internal register of peripheral. Now address has been placed so address decoder will select chip select line of the peripheral. Peripheral has to respond to CPU with data. Here peripheral has wait line to tell the CPU to wait for 1-2 Clock cycles. CPU will wait till wait is high. If peripheral is ready to supply data then peripheral has to pull wait line down and immediately should latch the data to data lines. Now CPU will read back data lines and with pull up nOE, read enable line. This way CPU tells that we are done with read. Now peripheral has to pull up wait and data line and it has to set it to high impedance state.
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Altera FPGA interfacing ARM, ARM CPU internals, ARM CPU, Cache Memory and MMU, ARM bus hierarchy, ARM data, address and control lines, ARM MMIO read, ARM MMIO write, FPGA interfacing with system bus, VHDL/Verilog program, ADS C Code, Linux Direct MMIO App, Linux Device Driver, Linux Application code, Final Demo,
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