ARM CPU internals - registers, mode of operations

ARM is Advanced RISC Machine. It has total 16 registers named as r0 to r15. r0 to r7 and r15 are general purpose registers and available for all processor modes. These registers are also called non-banked registers. r8-r14 are special registers and mode dependent registers. These registers are banked registers.

• r15 is program counter.
• r14-link register
• r13-stack pointer
• CPSR-Current Program Status Register
• SPSR-Saved Program Status Registers

ARM has modes of operations-

1. Normal (System & User)
2. FIQ – Fast Interrupt Request
3. Supervisor – Protected mode in Operating System
4. Abort – Data or Instruction Prefetch abort
5. IRQ- Interrupt Request
6. Undefined -Undefined execution state

Considering all modes and banked registers ARM has 37 registers in totality.

Now we will discuss about the instructions which are involved in read and write operations. ARM has load and store architecture for memory read write. Instructions like LOAD(B/W/L) and STR(B/W/L) are used. For immediate data movement ARM uses move(MOV) instruction. Say 0x10000000 is the address and we are reading a byte -

unsigned char *read_p = 0x10000000;
val = *read_p;

mov      r0,#0x10000000
ldrb     r6,[r0,#0]

Writing value to the address-

unsigned char *write_p = 0x10000000;
*write_p = val;
mov      r0,#0x10000000
strb     r6,[r0,#0]

‹ # ›